Simulation of Radix-2 Fast Fourier Transform Using Xilinx

The Radix-2 decimation-in-time Fast Fourier Transform is the simplest and most common form of the Cooley–Tukey algorithm. The FFT is one of the most widely used digital signal processing algorithms. It is used to compute the Discrete Fourier Transform and its inverse. It is widely used in noise reduction, global motion estimation and orthogonalfrequency-division-multiplexing systems such as wireless LAN, digital video broadcasting, digital audio broadcasting. It is described as the most important numerical algorithm of our lifetime. The number of applications for this transform continues to grow. The DecimationIn-Time radix-2 FFT using butterflies has designed. The butterfly operation is faster. The outputs of the shorter transforms are reused to compute many outputs, thus the total computational cost becomes less. The 32 bit input FFT is synthesized using Verilog. The simulation results and the implementation details such as design summary, RTL schematic and others can be noticed. The design is developed using hardware description language VHDL / Verilog on Xilinx 14.2 xc3s500E. KeywordsFast Fourier Transform (FFT); Decimation in Time (DIT); Radix-2